Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.3. Error Correction Signals

The error correction signals are present only when you turn on the ECC option.

Table 37.  Error Correction Signals
Signal Direction Width Description
ecc_err_det_corr Out 1 The MAC IP core can indicate detected and corrected ECC errors using the ecc_status register, or both the register and this signal.

This signal indicates the state of the ecc_status[0] register bit when the ecc_enable[0] register bit is set to 1. This signal is 0 when the ecc_enable[0] register bit is set to 1.

ecc_err_det_uncorr Out 1 The MAC IP core can indicate detected and uncorrected ECC errors using the ecc_status register, or both the register and this signal.

This signal indicates the state of the ecc_status[1] register bit when the ecc_enable[1] register bit is set to 1. This signal is 0 when the ecc_enable[1] register bit is set to 1.

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