Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

4.7. Reset Requirements

The MAC IP core consists of the following reset domains:

  • CSR reset—global reset,
  • MAC TX reset, and
  • MAC RX reset.

These resets are asynchronous events. When the MAC or any part of it goes into reset, the user application must manage possible asynchronous changes to the states of the MAC interface signals. The MAC does not guarantee any reset sequence. Intel recommends the sequence shown in the following diagram and table for CSR reset, and TX and RX datapaths reset respectively.

Figure 25. CSR Reset
Table 17.  TX and RX Datapaths Reset
No Stage Steps
1 Ensure no data transfer in progress.
  1. Set the tx_packet_control[0] bit to 1 to disable the TX datapath; the rx_transfer_control[0] bit to disable the RX datapath.
  2. Check the tx_transfer_status[8] bit for a value of 0 to ensure that no TX data transfer is in progress; the rx_transfer_status[8] bit for RX path. Alternatively, wait for a period of time.
2 Trigger reset.
  1. Ensure that the respective TX and RX clocks are stable.
  2. Assert the tx_rst_n signal or the rx_rst_n signal to reset the MAC TX or MAC RX respectively. You can also trigger the reset by setting the mac_reset_control[0] bit or the mac_reset_control[8] bit to 1 to reset the MAC TX or MAC RX respectively.
  3. Hold the reset signal active for at least three clock cycles.
3 Stop reset.
  1. Release the reset signal only when the clocks are stable.
  2. Wait for at least 500 ns to ensure the reset is fully complete.
  3. Clear the statistics counters.
4 Resume data transfer.
  1. Clear the tx_packet_control[0] bit to enable the TX datapath; the rx_transfer_control[0] bit to enable the RX datapath.
Note: During reset, the value of the avalon_st_tx_ready signal can be 0 or 1.

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