Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.6.1. Avalon® Streaming TX Data Interface Signals

Table 40.   Avalon® Streaming TX Data Interface Signals
Signal Direction Width Description
avalon_st_tx_startofpacket In 1 Assert this signal to indicate the beginning of the TX data.
avalon_st_tx_endofpacket In 1 Assert this signal to indicate the end of the TX data.
avalon_st_tx_valid In 1 Assert this signal to indicate that the avalon_st_tx_data[] signal and other signals on this interface are valid.
avalon_st_tx_ready Out 1 When asserted, indicates that the MAC IP core is ready to accept data. The reset value of this signal is non-deterministic.
Note: During reset, the value of the this signal can be 0 or 1.
avalon_st_tx_error In 1 Assert this signal to indicate that the current TX packet contains errors.
avalon_st_tx_data[] In 32/64 TX data from the client. The client sends the TX data to the MAC IP core in this order: avalon_st_tx_data[31:24], avalon_st_tx_data[23:16], and so forth.

The width is 64 bits when you enable the Use 64-bit Ethernet 10G MAC Avalon® streaming interface option. Otherwise, it is 32 bits

avalon_st_tx_empty[] In 2/3 Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data.
  • 0x0: All bytes are valid.
  • 0x1: The last byte is invalid.
  • 0x2: The last two bytes are invalid.
  • 0x3: The last three bytes are invalid.
The width is 3 bits when you enable the Use 64-bit Ethernet 10G MAC Avalon® streaming interface option. Otherwise, it is 2 bits.

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