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1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
2.4. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor)
2.6. Simulating Intel® FPGA IP Cores
2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5.1. Register Map
5.2. Register Access Definition
5.3. Primary MAC Address
5.4. MAC Reset Control Register
5.5. TX Configuration and Status Registers
5.6. Flow Control Registers
5.7. Unidirectional Control Registers
5.8. RX Configuration and Status Registers
5.9. Timestamp Registers
5.10. ECC Registers
5.11. Statistics Registers
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Unidirectional Signals
6.5. Avalon® Memory-Mapped Interface Programming Signals
6.6. Avalon® Streaming Data Interfaces
6.7. Avalon® Streaming Flow Control Signals
6.8. Avalon® Streaming Status Interface
6.9. PHY-side Interfaces
6.10. IEEE 1588v2 Interfaces
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4.6.2. Priority-Based Flow Control
Follow these steps to use the priority-based flow control (PFC):
- Turn on the Priority-based flow control (PFC) parameter and specify the number of priority levels using the Number of PFC priorities parameter. You can specify between 2 to 8 PFC priority levels.
- Set the following registers.
- On the TX datapath:
- Set tx_pauseframe_enable to 0 to disable the IEEE 802.3 flow control.
- Set tx_pfc_priority_enable[n] to 1 to enable the PFC for priority queue n.
- On the RX datapath:
- Set the IGNORE_PAUSE bit in the rx_frame_control register to 1 to disable the IEEE 802.3 flow control.
- Set the rx_pfc_control[7:0] register bits to 0 to enable the PFC. Most of the rest of the bits are unused.
- On the TX datapath:
- Connect the avalon_st_tx_pfc_gen_data signal to the corresponding RX client logic and the avalon_st_rx_pfc_pause_data signal to the corresponding TX client logic.
- You have the option to configure the MAC RX to forward the PFC frame to the client by setting the rx_pfc_control[16] register to 1. By default, the MAC RX drops the PFC frame after processing it.
You must handle the XON/XOFF requests in the following manner:
- Assert the XOFF, which runs at the clock frequency of 312.5 MHz, for at least 1 clock cycle, which runs at the clock frequency of 312.5 MHz to ensure that the PFC frame can transfer successfully.
- Assert the XON, which runs at the clock frequency of 312.5 MHz, for at least 25 clock cycle to ensure that the PFC frame can transfer successfully.