- Corrected the Intel Cyclone 10 GX device speed grades:
- With 1588 feature: Corrected speed grade values from -I2, -E2 to -I5, -E5.
- Without 1588 feature: Corrected speed grade values from -I3, -E3 to -I6, -E6.
- Updated Figure: PHY Configuration with 10GBASE-R with IEEE 1588v2 Enabled for Intel Stratix 10 Devices
- Updated the decription in the 10GBASE-R Register Mode topic:
- Added support for Intel Stratix 10 devices.
- Added Figure: PHY Configuration with 10GBASE-R with IEEE 1588v2 Enabled for Intel Stratix 10 Devices.
- Renamed the document as Intel FPGA Low Latency Ethernet 10G MAC User Guide.
- Added support for the Intel Cyclone 10 GX device family.
- Added a new feature—Peer-to-Peer:
- Added a new parameter—Enable peer-to-peer support.
- Updated the description in the TX Datapath sub-topic of the IEEE 1588v2 topic.
- Added new timestamp registers:
- Added new IEEE 1588v2 Egress TX signals—tx_egress_p2p_update and tx_egress_p2p_val.
- Added new IEEE 1588v2 Ingress RX signals—rx_ingress_p2p_val and rx_ingress_p2p_val_valid.
- Updated the About LL Ethernet 10G MAC section:
- Updated the Features topic.
- Updated the "Device Family Support for LL 10GbE MAC" table: Updated the support for Intel Arria 10 and Intel Cyclone 10 GX device families from Preliminary to Final.
- Updated the "Device Family Support for Configurations" table: Updated the configuration support for Intel Stratix 10 and Intel Cyclone 10 GX device families.
- Updated the Getting Started section:
- Updated Creating a Signal Tap Debug File to Match Your Design Hierarchy topic.
- Updated the Parameter Settings for the LL Ethernet 10G MAC IP Core topic:
- Updated the descriptions of the Enable ECC on memory blocks, Enable time stamping, , Enable asymmetry support, Timestamp fingerprint width, and Time of Day Format parameters.
- Added Jitter on PLL Clocks topic.
- Updated the Functional Description section:
- Updated the Payload Length topic.
- Updated the 10GBASE-R Register Mode topic: Added a note to clarify that 10GBASE-R register mode is not supported in Intel Stratix 10 devices.
- Updated the Configuration Registers section:
- Updated the "Timestamp Registers" table: Updated the descriptions for the tx_fns_adjustment_10G, tx_ns_adjustment_10G, rx_fns_adjustment_10G, rx_ns_adjustment_10G, tx_fns_adjustment_mult_speed, tx_ns_adjustment_mult_speed, rx_fns_adjustment_mult_speed, and rx_ns_adjustment_mult_speed registers.
- Updated "Hardware PMA Delay" table: Updated the RX latency values for Intel Stratix 10 devices.
- Updated for latest branding standards.
- Made editorial updates throughout the document.
- Added support for two new variants:
- Updated the following tables:
- Features Comparison
- Device Family Support for Configurations
- Updated the Interface Signals figure.
- Device Family Support forUpdated the operating modes for the clock and reset signals in the Clock and Reset Signals table.
- Updated descriptions and tables for the following topics:
- Parameter Settings for the LL Ethernet 10G MAC IP Core
- Unidirectional Signals
- XGMII TX Signals
- XGMII RX Signals
- GMII TX Signals
- GMII RX Signals
- MII TX Signals
- MII RX Signals
- IEEE 1588v2 Ingress TX Signals
- IEEE 1588v2 Ingress RX Signals
- Added unidirectional_force_remote_fault signal in the Unidirectional Signals table.
- Made minor editorial updates.
- Clarified the device family support for Stratix 10 devices.
- Updated the Features topic.
- Updated the Device Family Support topic:
- Added Intel FPGA IP Core Device Support Levels table.
- Updated the LL Ethernet 10G MAC table to include Stratix 10 speed grades with 1588 feature.
- Removed the Definition: Device Support Level topic.
- Updated the Device Family Support for Configurations table to include additional configurations that support Stratix 10 device family:
- 1G/2.5G/10G MAC with 1G/2.5G/10G Multi-rate Ethernet PHY
- 1G/2.5G/10G MAC with 1G/2.5G/10G Multi-rate Ethernet PHY and IEEE 1588v2
- 1G/2.5G MAC with 1G/2.5G Multi-rate Ethernet PHY
- 1G/2.5G MAC with 2.5G Multi-rate Ethernet PHY
- 10M/100M/1G/10G MAC with IEEE 1588v2
- 1G/10G MAC with Backplane Ethernet 10GBASE-KR PHY
- Added tables listing resource utilization for Arria 10 and Stratix 10 devices in the Resource Utilization topic.
- Updated the Hardware PMA Delay table to include support for Stratix 10 device family.
- Updated the TX Configuration and Status Registers table:
- Revised the HW Reset Value of tx_ipg_10g from 0x0 to 0x1.
- Revised the HW Reset Value of tx_ipg_10M_100M_1G from 0x0 to 0x0C.
- Added tables listing LX and RX latency values for Arria 10 and Stratix 10 devices in the TX and RX latency topic.
- Updated the Timestamp Registers table to map registers in order of address.
- Updated the Clock and Reset Signals table.
- Updated the description for speed_sel signal in the Speed Selection table.
- Updated the width and description for csr_address in the Avalon-MM Programming Signals table.
- Updated the width and description for avalon_st_tx_data signal in both Avalon-ST TX Data Interface Signals and Avalon-ST RX Data Interface Signals tables.
- Updated Typical Client Frame at TX Interface figure, Endian Conversion figure, and Typical Client Frame at Receive Interface figure.
- Added support for the Stratix 10 device family.
- Added 1588 asymmetry support feature.
- Corrected the Arria 10 device speed grades from –C2 and –C3 to –E2 and –E3.
- Updated the topic about XGMII encapsulation in the TX datapath to clarify that the MAC TX converts the eighth byte of the preamble to a 1-byte SFD.
- Added a table listing the MAC behavior for different frame types in the topic about frame type checking.
- Updated the topic listing the clock and reset signals to specify the clock domains of the tx_rst_n and rx_rst_n signals.
- Updated the avalon_st_txstatus_data signal description to clarify that the status is only valid if the TX frame is valid.
- Updated the description of avalon_st_txstatus_error to clarify that this bit asserts if the avalon_st_tx_error input signal from client is asserted.
- Added tables listing the clocks for the Avalon® -ST and IEEE 1588v2 interface signals.
- Added the different word offsets for the tx_ipg_10g, tx_ipg_10M_100M_1G, ecc_status, ecc_enable, and mac_reset_control registers if you turn on Use legacy Ethernet 10G MAC Avalon Memory-Mapped interface.
- Updated document template.
- Updated the following topics to include the new speed mode 1G/2.5G/5G/10G (USXGMII): Features, Device Family Support, Parameter Settings, XGMII TX, and XGMII RX.
- Added a new topic: LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC.
- Added a new topic: Creating a SignalTap II Debug File to Match Your Design Hierarchy.
- Updated the description of the Overflow Handling.
- Replace the timing diagram in the XGMII Error Handling topic.
- Revised the description of invalid frames in the Statistics Registers topic and removed the tx_stats_etherStatsCRCErr, tx_stats_etherStatsJabbers, tx_stats_etherStatsFragments, and tx_stats_framesCRCErr from the topic.
- Removed the PMA Delay from Simulation Model table from the Calculating Timing Adjustment topic because simulation data is not deterministic.
- Updated the Features, Device Family Support, Configuration Registers, and Interface Signals topics for 1G/2.5G and 1G/2.5G/10G operating speeds.
- Updated the Resource Utilization table.
- Revised the description in the Upgrading Outdate IP Cores topic.
- Updated the Reset topic, added a step in stage 2.
- Updated the Register Access topic, ECC status, and statistics clear register definitions.
- Updated the tx_unidir_control register to include support for user-triggered remote fault notification.
- Removed the Migrating IP Cores to a Different Device topic.
- Update the Device Support table.
- Updated the Resource Utilization table.
- Updated the Parameter Settings table.
- Added instruction on how to read statistics counters in the Statistics Registers topic.
- Added new registers: tx_vlan_detection, rx_vlan_detection, tx_ipg_10g, tx_ipg_10M_100M_1G, tx_transfer_status, and rx_transfer_status.
- Updated the description of the rx_stats_octetsOK and tx_stats_octetsOK statistics counters.
- Update the Length Checking topic.
- Added the Reset Requirements topic.
- Added the Deriving TX Timing Adjustments and Deriving RX Timing Adjustments topics.
- Removed the Minimum Inter-packet Gap topic.
- Updated the Performance and Resource Utilization table—improved the resource utilization for IEEE 1588v2 feature.
- Added a new feature—10GBASE-R register mode:
- Added a new parameter—Enable 10GBASE-R register mode.
- Added new signals—tx_xcvr_clk, rx_xcvr_clk, xgmii_tx_valid, xgmii_rx_valid.
- Added new parameter options for Time of Day Format.
- Added a new table in the Frame Type Checking topic to describe the MAC behavior for different frame types.
- Added a new table—Register Access Type Convention—to describe the access type for the IP core registers.
- Added a new section about timing constraints.
- Revised the receive timestamp registers word offset to start from 0x0120 to 0x012C.
- Added a recommendation for the csr_rst_n signal—deassert the csr_rst_n signal at least once after tx_clk and rx_clk are stable.
- Revised the number of bits for fractional number of clock cycle for rx_path_delay_10g_data and rx_path_delay_1g_data signals to Bit [9:0]: Fractional number of clock cycle, Bit [21/15:10]:Number of clock cycle.
- Updated the signals description for:
- Improved the performance and resource utilization.
Added a new feature—Unidirectional Ethernet.
- Added a new parameter—Enable Unidirectional feature.
- Added Unidirectional registers and signals.
- Added information about PMA analog and digital delay for IEEE 1588v2 MAC registers.
- Edited the bit description of avalon_st_rxstatus_error signal.
- Added more information about the avalon_st_pause_data bit signal to indicate that the transmission of XON pause frames only trigger for one time after XOFF pause frames regardless of how long the avalon_st_pause_data is asserted.
- Updated the statistics registers description.
- Edited the bit description of tx_underflow_counter0, tx_underflow_counter1, rx_pktovrflow_etherStatsDropEvents,rx_pktovrflow_error signals.
- Edited the bit description of csr_clk signal to state that the recommended clock frequency for this signal is 125 Mhz–156.25 Mhz regardless of whether you select register-based or memory-based statistics counter.
- Updated the tx_rst_n and rx_rst_n signals description to reflect the change from asynchronous reset to synchronous reset.
- Updated the csr_waitrequest signal description.