Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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5.6. Flow Control Registers

Table 26.  Flow Control Registers
Word Offset Register Name Description Access HW Reset Value
0x0040 tx_pauseframe_control
  • Bits 1:0—configures the transmission of pause frames.

    00: No pause frame transmission.

    01: Trigger the transmission of an XON pause frame (pause quanta = 0), if the transmission is not disabled by other conditions.

    10: Trigger the transmission of an XOFF pause frame (pause quanta = tx_pauseframe_quanta register), if the transmission is not disabled by other conditions.

    11: Reserved. This setting does not trigger any action.

  • Bits 31:2—reserved.

Changes to this self-clearing register affects the next transmission of a pause frame.

RW 0x0
0x0042 tx_pauseframe_quanta
  • Bits 15:0—pause quanta in unit of quanta, 1 unit = 512 bits time. The MAC IP core uses this value when it generates XOFF pause frames. An XOFF pause frame with a quanta value of 0 is equivalent to an XON frame.
  • Bits 31:16—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x0
0x0043 tx_pauseframe_holdoff_quanta
  • Bits 15:0—specifies the gap between two consecutive transmissions of XOFF pause frames in unit of quanta, 1 unit = 512 bits time. The gap prevents back-to-back transmissions of pause frames, which may affect the transmission of data frames.
  • Bits 31:16—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x1
0x0044 tx_pauseframe_enable
  • Bit 0—configures the transmission of pause frames. This bit affects pause frame requests from both register and vector settings.

    0: Disables pause frame transmission.

    1: Enables pause frame transmission, if TX path is enabled by tx_packet_control.

  • Bits 2:1—specifies the trigger for pause frame requests.

    00: Accepts pause frame requests only from vector setting, avalon_st_pause_data.

    01: Accepts pause frame requests only from register setting, tx_pauseframe_control.

    10 / 11: Reserved.

  • Bits 31:3—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x1
0x0046 tx_pfc_priority_enable 8 Enables priority-based flow control on the TX datapath.
  • Bits 7:0—setting bit n enables priority-based flow control for priority queue n. For example, setting tx_pfc_priority_enable[0] enables queue 0.
  • Bits 31:8—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x0
0x0048 pfc_pause_quanta_0 8 Specifies the pause quanta for each priority queue.
  • Bits 15:0—pfc_pause_quanta_n[15:0] specifies the pause length for priority queue n in quanta unit, where 1 unit = 512 bits time.
  • Bits 31:16—reserved.

Configure these registers before you enable the MAC IP core for operations.

RW 0x0
0x0049 pfc_pause_quanta_1 8
0x004A pfc_pause_quanta_2 8
0x004B pfc_pause_quanta_3 8
0x004C pfc_pause_quanta_4 8
0x004D pfc_pause_quanta_5 8
0x004E pfc_pause_quanta_6 8
0x004F pfc_pause_quanta_7 8
0x0058 pfc_holdoff_quanta_0 8 Specifies the gap between two consecutive transmissions of XOFF pause frames in unit of quanta, 1 unit = 512 bits time. The gap prevents back-to-back transmissions of pause frames, which may affect the transmission of data frames.
  • Bits 15:0— pfc_holdoff_quanta_n[15:0] specifies the gap for priority queue n.
  • Bits 31:16—reserved.

Configure these registers before you enable the MAC IP core for operations.

RW 0x1
0x0059 pfc_holdoff_quanta_1 8
0x005A pfc_holdoff_quanta_2 8
0x005B pfc_holdoff_quanta_3 8
0x005C pfc_holdoff_quanta_4 8
0x005D pfc_holdoff_quanta_5 8
0x005E pfc_holdoff_quanta_6 8
0x005F pfc_holdoff_quanta_7 8
8 This register is used only when you turn on the Enable preamble pass-through mode option. It is reserved when not used.