Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.9.3. GMII TX Signals

Table 48.  GMII TX Signals
Signal Operating Mode Direction Width Description
gmii_tx_clk
  • 1G/10G
  • 10M/100M/1G/10G
In 1 125 MHz TX clock.
gmii_tx_d[] Out 8 TX data.
gmii_tx_en Out 1 When asserted, indicates the TX data is valid.
gmii_tx_err Out 1 When asserted, indicates the TX data contains error.
gmii16b_tx_clk
  • 1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
In 1 156.25 MHz TX clock for 2.5G; 62.5 MHz TX clock for 1G; 62.5 MHz TX clock for 10M/100M/1G.
gmii16b_tx_d[] Out 16 TX data.
gmii16b_tx_en Out 2 When asserted, indicates the TX data is valid.
gmii16b_tx_err Out 2 When asserted, indicates the TX data contains error.