Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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4.6.2.2. PFC Frame Transmission

PFC frame generation is triggered through the avalon_st_tx_pfc_gen_data signal. Set the respective bits to generate XOFF or XON requests for the priority queues.

For XOFF requests, you can configure the pause quanta for each priority queue using the pfc_pause_quanta_n registers. For an XOFF request for priority queue n, the MAC TX sets bit n in the Pause Quanta Enable field to 1 and the Pause Quanta n field to the value of the pfc_pause_quanta_n register. You can also configure the gap between successive XOFF requests for a priority queue using the pfc_holdoff_quanta_n register.

For XON requests, the MAC TX sets the pause quanta to 0. You must generate a XOFF request before generating a XON request.