Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.1. Clock and Reset Signals

The LL Ethernet 10G MAC Intel® FPGA IP core operates in multiple clock domains. You can use different sources to drive the clock and reset domains. You can also use the same clock source as specified in the description of each signal.

Table 35.  Clock and Reset Signals
Signal Operating Mode Direction Width Description
tx_312_5_clk 10G, 1G/10G,1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G/10G In 1 312.5 MHz clock for the MAC TX datapath when the Enable 10GBASE-R register mode is disabled. You may use the same clock source for this clock and rx_312_5_clk.
tx_xcvr_clk 10G In 1 322.265625 MHz clock for the MAC TX datapath when the Enable 10GBASE-R register mode is enabled.
tx_156_25_clk 10G, 1G/10G,1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G/10G In 1

156.25 MHz clock for the MAC TX datapath when you choose to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming TX data interface or XGMII. This feature is not available when the Enable 10GBASE-R register mode is enabled.

Intel recommends that this clock and tx_312_5_clk share the same clock source. This clock must be synchronous to tx_312_5_clk. Their rising edges must align and must have 0 ppm and phase-shift.

1G/2.5G, 10M/100M/1G/2.5G In 1 156.25 MHz clock for the Avalon® streaming TX data interface.
tx_rst_n All In 1

Active-low asynchronous reset in the tx_312_5_clk clock domain for the MAC TX datapath.

For the reset requirements, refer to the related links.

rx_312_5_clk 10G, 1G/10G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G/10G In 1 312.5 MHz clock for the MAC RX datapath when the Enable 10GBASE-R register mode is disabled. You may use the same clock source for this clock and tx_312_5_clk.
rx_xcvr_clk 10G In 1 322.265625 MHz clock for the MAC RX datapath when the Enable 10GBASE-R register mode is enabled.
rx_156_25_clk 10G, 1G/10G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G/10G In 1

156.25MHz clock for the MAC RX datapath when you choose to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming RX data interface or XGMII. This feature is not available when the Enable 10GBASE-R register mode is enabled.

Intel recommends that you use the same clock source for this clock and rx_312_5_clk. This clock must be synchronous to rx_312_5_clk. Their rising edges must align and must have 0 ppm and phase-shift.

1G/2.5G, 10M/100M/1G/2.5G In 1 156.25 MHz clock for the Avalon® streaming RX data interface.
rx_rst_n All In 1

Active-low reset in the rx_312_5_clk clock domain for the MAC RX datapath.

For the reset requirements, refer to the related links.

csr_clk 10G, 1G/10G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G/10G In 1 Clock for the Avalon® memory-mapped control and status interface. Intel recommends that this clock operates within 125 - 156.25 MHz. A lower frequency might result in inaccurate statistics especially when you are using register-based statistics counters.
1G/2.5G, 10M/100M/1G/2.5G In 1 125 MHz clock for the Avalon® memory-mapped control and status interface.
csr_rst_n All In 1

Active-low asynchronous reset signal for the csr_clk domain. This signal acts as a global reset for the MAC IP core.

For the reset requirements, refer to the related links.

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