Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Download
Document Table of Contents

2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface

Follow these steps to implement 32-bit datapath on the Avalon® streaming and Avalon® memory-mapped interfaces.
  1. Instantiate the LL Ethernet 10G MAC Intel® FPGA IP core in your design. If you are using a PHY with 64-bit SDR XGMII interface, turn on the Use legacy Ethernet 10G MAC XGMII Interface option.
  2. Modify your user logic to accommodate 32-bit datapaths on Avalon® streaming TX and RX data interfaces.
  3. Ensure that tx_312_5_clk and rx_312_5_clk are connected to 312.5 MHz clock sources. Intel recommends that you use the same clock source for these clock signals.
  4. Update the register offsets to the offsets of the LL Ethernet 10G MAC Intel® FPGA IP core. The configuration registers of the LL Ethernet 10G MAC Intel® FPGA IP core allow access to new features such as error correction and detection on memory blocks.
  5. If you turn on the Use legacy Ethernet 10G MAC XGMII Interface option, add a 156.25 MHz clock source for tx_156_25_clk and rx_156_25_clk. This 156.25 MHz clock source must be rise-to-rise synchronous to the 312.5 MHz clock source.
  6. Ensure that csr_clk is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be accurate.