Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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Document Table of Contents

1.1. Features

This Intel® FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard available on the IEEE website (www.ieee.org). All LL 10GbE Intel® FPGA IP core variations include MAC only and are in full-duplex mode. These Intel® FPGA IP core variations offer the following features:

  • MAC features:
    • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
    • Three variations for selected operating modes: MAC TX only block, MAC RX only block, and both MAC TX and MAC RX block.
    • 10GBASE-R register mode on the TX and RX datapaths, which enables lower latency.
    • Programmable promiscuous (transparent) mode.
    • Unidirectional feature as specified by IEEE 802.3 (Clause 66).
    • Priority-based flow control (PFC) with programmable pause quanta. PFC supports 2 to 8 priority queues.
  • Interfaces:
    • Client-side—32-bit Avalon® streaming interface.
    • Management—32-bit Avalon® memory-mapped interface.
    • PHY-side—32-bit XGMII for 10 GbE, 16-bit GMII for 2.5 GbE, 8-bit GMII for 1 GbE, or 4-bit MII for 10M/100M.
  • Frame structure control features:
    • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
    • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
    • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications.
    • Supports programmable IPG.
    • Ethernet flow control using pause frames.
    • Programmable maximum length of TX and RX data frames up to 64 Kbytes (KB).
    • Preamble passthrough mode on TX and RX datapaths, which allows user defined preamble in the client frame.
    • Optional padding insertion on the TX datapath and termination on the RX datapath.
  • Frame monitoring and statistics:
    • Optional CRC checking and forwarding on the RX datapath.
    • Optional statistics collection on TX and RX datapaths.
  • Optional timestamping as specified by the IEEE 1588v2 standard for the following configurations:
    • 10GbE MAC with 10GBASE-R PHY IP core
    • 1G/10GbE MAC with 1G/10GbE PHY IP core
    • 1G/2.5GbE MAC with 1G/2.5G Multi-rate Ethernet PHY IP core
    • 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multi-rate Ethernet PHY IP core
    • 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core