Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.2. Speed Selection Signal

Table 36.  Speed Selection Signal
Signal Operating Mode Direction Width Description
speed_sel 10G, 1G/10G,10M/100M/1G/10G In 2

Connect this asynchronous signal to the PHY to obtain the PHY's speed:

  • 0x0 = 10 Gbps
  • 0x1 = 1 Gbps
  • 0x2 = 100 Mbps
  • 0x3 = 10 Mbps
  • 0x4 = 2.5 Gbps
  • 0x5 = 5 Gbps

The speed_sel signal can be synchronized to TX or RX clock of the LL Ethernet 10G MAC Intel® FPGA IP core.

Before the speed change, make sure the MAC TX and RX datapaths are idle with no packet transmission.

After the line rate changes, trigger a reset on the TX and RX datapaths by asserting these active-low reset signals, tx_rst_n and rx_rst_n.

1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G In 3

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