6.2. Speed Selection Signal
Connect this asynchronous signal to the PHY to obtain the PHY's speed:
The speed_sel signal can be synchronized to TX or RX clock of the LL Ethernet 10G MAC Intel® FPGA IP core.
Before the speed change, make sure the MAC TX and RX datapaths are idle with no packet transmission.
After the line rate changes, trigger a reset on the TX and RX datapaths by asserting these active-low reset signals, tx_rst_n and rx_rst_n.
|1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G||In||3|