Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

5.7. Unidirectional Control Registers

Table 27.  Unidirectional Control Registers
Word Offset Register Name Description Access HW Reset Value
0x0070 tx_unidir_control 9
  • Bit 0—configures the unidirectional feature on the TX path.

    0: Disables unidirectional feature.

    1: Enables unidirectional feature.

  • Bit 1—configures remote fault sequence generation when the unidirectional feature is enabled on the TX path.

    0: Enable remote fault sequence generation on detecting local fault.

    1: Disable remote fault sequence generation.

  • Bit 2—configures user-triggered remote fault notification when the unidirectional feature is enabled on the TX path.

    0: Default setting.

    1: The IP core sends remote fault notifications continuously until this bit is cleared.

  • Bits 31:3—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x0
9 This register is used when you turn on Enable unidirectional feature. It is reserved when not used.

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