Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.9.4. GMII RX Signals

Table 49.  GMII RX Signals
Signal Operating Mode Direction Width Description
gmii_rx_clk
  • 1G/10G
  • 10M/100M/1G/10G
In 1 125 MHz RX clock.
gmii_rx_d[] In 8 RX data.
gmii_rx_dv In 1 When asserted, indicates the RX data is valid.
gmii_rx_err In 1 When asserted, indicates the RX data contains error.
gmii16b_rx_clk
  • 1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
In 1 156.25 MHz RX clock for 2.5G; 62.5 MHz RX clock for 1G; 62.5 MHz RX clock for 10M/100M/1G.
gmii16b_rx_d[] In 16 RX data.
gmii16b_rx_dv In 2 When asserted, indicates the RX data is valid.
gmii16b_rx_err In 2 When asserted, indicates the RX data contains error.