Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Download
Document Table of Contents

4.8.1. 10GBASE-R Register Mode

The MAC IP core supports this feature for use with the Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Transceiver Native PHY IP core preset configurations. When operating in this mode, the round-trip latency for the MAC and PHY is reduced to 140 ns (for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) or 168 ns (for Intel® Stratix® 10 devices) with a slight increase in resource count and clock frequencies.

When you enable this feature, the MAC IP core implements two additional signals to determine the validity of the data on the TX and RX XGMII. These signals, xgmii_tx_valid and xgmii_rx_valid, ensure that the effective data rate of the MAC is 10 Gbps. You must also observe the following guidelines when using the register mode:

  • For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the selected preset is 10GBASE-R Register Mode.
  • For Intel® Stratix® 10 devices, the selected preset is 10GBASE-R 1588.
  • The PHY must expose the TX and RX parallel clocks.
  • The PHY must expose data valid signals, with MAC/PHY TX/RX interfaces in register mode, as in the IEEE 1588v2 configuration.
  • The MAC and PHY run at the parallel clock frequency of 322.265625 MHz (the PCS/PMA width equals to 32).
Figure 26. PHY Configuration with 10GBASE-R Register Mode Enabled for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices


Figure 27. PHY Configuration with 10GBASE-R with IEEE 1588v2 Enabled for Intel® Stratix® 10 Devices