Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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2.10.2. Timing Constraints

Intel provides timing constraint files (.sdc) to ensure that the IP core meets the design timing requirements in Intel FPGA devices. The files constraint the false paths and multicycle paths in the IP core. The timing constraints files are specified in the <variation_name> .qip file and is automatically included in the Intel® Quartus® Prime project files.
The timing constraints files are in the IP directory. You can edit these files as necessary. They are for clock crossing logic and grouped as below:
  • Pseudo-static CSR fields
  • Clock crosser
  • Dual clock FIFO
Note: For the IP core to work correctly, there must be no other timing constraints files cutting or overriding the paths, for example, set_false_path, set_clock_groups, at the project level.
Note: If you enable IEEE 1588v2 in 10G speed, Intel® recommends that you add the following constraint in the Intel® Quartus® Prime Settings File (.qsf):
set_instance_assignment -name GLOBAL_SIGNAL OFF -to
"*|alt_em10g32:alt_em10g32_0|alt_em10g32_clk_rst:clk_rst_inst|alt_em10g32_rst_cnt:tx_reset_count_inst|rst_n_out"