Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.6.2. Avalon® Streaming RX Data Interface Signals

Table 41.   Avalon® Streaming RX Data Interface Signals
Signal Direction Width Description
avalon_st_rx_startofpacket Out 1 When asserted, indicates the beginning of the RX data.
avalon_st_rx_endofpacket Out 1 When asserted, indicates the end of the RX data.
avalon_st_rx_valid Out 1 When asserted, indicates that the avalon_st_rx_data[] signal and other signals on this interface are valid.
avalon_st_rx_ready In 1 Assert this signal when the client is ready to accept data.
avalon_st_rx_error[] Out 6 This signal indicates one or more errors in the current packet being transferred on the Avalon® streaming RX interface. It is qualified by the avalon_st_rx_valid and avalon_st_rx_ready signals and aligned to the end of packet.
  • Bit 0—PHY error.
    • For 10 Gbps, the data on xgmii_rx_data contains a control error character (FE).
    • For 10 Mbps,100 Mbps,1 Gbps, gmii_rx_err or mii_rx_err is asserted.
    • For 1G/2.5G, gmii16b_rx_err is asserted.
  • Bit 1—CRC error. The computed CRC value does not match the CRC received.
  • Bit 2—Undersized frame. The RX frame length is less than 64 bytes.
  • Bit 3—Oversized frame.
  • Bit 4—Payload length error.
  • Bit 5—Overflow error. The user application is not ready to receive more data while still receiving incoming data from the MAC IP core.
avalon_st_rx_data[] Out 32/64 RX data to the client. The MAC IP core sends the RX data to the client in this order: avalon_st_rx_data[31:24], avalon_st_rx_data[23:16], and so forth.

The width is 64 bits when you enable the Use 64-bit Ethernet 10G MAC Avalon® streaming interface option. Otherwise, it is 32 bits

avalon_st_rx_empty[] Out 2/3

Contains the number of empty bytes during the cycle that contain the end of the RX data.

The width is 3 bits when you enable the Use 64-bit Ethernet 10G MAC Avalon® streaming interface option. Otherwise, it is 2 bits.