DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

3.4. Verifying your DSP Builder Design with C++ Software Models

You can generate C++ software models for designs that support bit-accurate or bit-and-cycle-accurate simulation except for designs that contain bus blocks. The C++ software models simulate a design as it functions on the hardware - they are not purely algorithmic models. The models operate in the same way as the DSP Builder design operates on the FPGA hardware. For example, the software models have the same latency as the design.