DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Document Table of Contents

6.4.18. Super-Sample Fractional FIR Filter

This design example shows how the filters cope with data rates greater than the clock rate. The design example uses the FractionalFIR block to build a single channel interpolate by 3, decimate by 2, symmetrical, 33-tap FIR filter.

The input sample rate is two times the clock rate. The filter upconverts the input sample rate to three times the clock rate, which is visible in the vector input and output data connections. The input receives two samples in parallel at the input, and three samples are output each cycle.

The model file is demo_ssfirf.mdl.