DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

6.4.7. Fractional-Rate FIR Filter

This design example implements a fractional rate FIR filter.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_firf.m script.

The FilterSystem subsystem includes the Device and FractionalRateFIR blocks.

The model file is demo_firf.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.