DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents Real-Time Hardware Verification Design Example

You can verify your DSP Builder design in hardware by sampling real-time data with the demo_sil_nco design example. This design uses a MATLAB app GUI to control and capture real-time data from an NCO running at full clock rate in an FPGA.

The MATLAB app GUI uses the DSP Builder System Console API to set the desired frequency and capture sample data in a loop. The design:

  1. Triggers capture
  2. Polls data ready register
  3. Reads captured data
  4. Uses MATLAB to calculate and plot an FFT
Figure 32. NCO
Figure 33. Capture buffers with control registers
Figure 34. Address and capture logic
Figure 35. Platform Designer system
Figure 36. MATLAB App GUI to Control and Visualize Hardware using System Console