DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Document Table of Contents

6.2.26. Variable-Size Supersampled FFT with Bit-Reverse

This DSP Builder design example implements a variable-size supersampled FFT, with sizes ranging from 256 to 2,048 points, and a parallelism of 4 wires.

The incoming data is of fixed-point type and it both arrives and departs in natural order. The number of radix-2 stages assigned to the serial section of the hybrid FFT is 7.

The MultiwireVariableBitReverse block configuration supports sizes up to the maximum 2,048.

This design example also demonstrates channel values alongside each FFT.

The model file is demo_variable_br_hybridfft.mdl.