DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

6.4.17. Super-Sample Decimating FIR Filter

This design example shows how the filters cope with data rates greater than the clock rate. The design example uses the DecimatingFIR block to build a single channel decimate by 2, symmetrical, 33-tap FIR filter.

The input sample rate is six times the clock rate. The filter decimates by two the input sample rate to three times the clock rate, which is visible in the vector input and output data connections. The input receives six samples in parallel at the input, and three samples are output each cycle.

After simulation, you can view the resource usage.

The model file is demo_ssfird.mdl.