DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Public
Document Table of Contents

13.2.1. Avalon-ST Input (AStInput)

Place this block at the front end of a system to generate the appropriate hw.tcl code for an Avalon Streaming interface with same name as the name of this block.
Table 90.  AStInput Block External Interface Signals
Name Direction Description
sink_channel input Channel number.
sink_data input The data (which may be, or include control data).
sink_eop input Indicates end of packet.
sink_ready output Indicates to upstream components that the DSPBA component can accept sink_data on this rising clock edge.
sink_sop input Indicates start of packet.
sink_valid input Indicates that sink_data, sink_channel, sink_sop, and sink_eop are valid.
Table 91.  AStInput Block Internal Interface Signals
Name Direction Description
input_channel output Channel number.
input_data output The data (which may be, or include control data).
input_eop output Indicates end of packet.
input_ready input Indicates from the output of the DSP Builder component that it can accept sink_data on this rising clock edge.
input_sop output Indicates start of packet.
input_valid output Indicates that input_data, input_channel, input_sop and input_eop are valid.