DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Public
Document Table of Contents

4.2. Setting the Parameters on the Testbench Source Blocks

Set the testbench parameters to finish the DSP Builder Fibonacci design.

Procedure

  1. Double-click on the Real block to display the Source Block Parameters dialog box.
  2. Set the Vector of output values to [0 1 1 1 zeros(1,171)].' in the Main tab.
  3. Switch to the Editor window for setup_my_fibonacci.m.
  4. Change the parameters to:
    • my_fibonacci_param.ChanCount = 1;
    • my_fibonacci_param.SampleRate = fibonacci_param.ClockRate;
    • my_fibonacci_param.input_word_length = 1;
    • my_fibonacci_param.input_fraction_length = 0;
  5. In the top-level design, delete the ChannelView, the Scope Deserialized Outputs scope and any dangling connections.
  6. Double-click the Convert block and make the input unsigned by changing:
    fixdt(1,fibonacci_param.input_word_length,fibonacci_param.input_fraction_length)

    to:
    
fixdt(0,fibonacci_param.input_word_length,fibonacci_param.input_fraction_length)
  7. Save the Fibonacci model.
    Figure 40. Completed Fibonacci Model