DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents

14.5.5. Synthesis Information (SynthesisInfo)

Use the SynthesisInfo block to set the synthesis mode and label a primitive subsystem as the top-level synthesizable subsystem. DSP Builder flattens and synthesizes the subsystem, and all those subsystems below as a unit. Primitive subsystems must have a SynthesisInfo block. DSP Builder creates pipelines and redistributes memories optimally to achieve the desired clock frequency. The SynthesisInfo block controls the synthesis flow for the current model.

The inputs and outputs to this subsystem become the primary inputs and outputs of the RTL entity that DSP Builder creates.

The SynthesisInfo block can be at the same level as the Device block (if the synthesizable subsystem is the same as the generated hardware subsystem). However, it is often convenient to create a separate subsystem level that contains the Device block. Refer to the design examples for some examples of design hierarchy.

Figure 118.  SynthesisInfo Parameters
Table 275.  Parameters for the SynthesisInfo Block
Parameter Description
Constrain Latency Select the block types to which DSP Builder applies the latency constraint: Channel-In to Channel-Out or GPIn-to-GPOut. You can select the type of constraint and specify its value. The value can be a workspace variable or an expression but must evaluate to a positive integer.

You can select the following types of constraint:

  • >: Greater than
  • >=: Greater than or equal to
  • =: Equal to
  • <=: Less than or equal to
  • <: Less than

Select either + or - and enter an expression (refer to Dependent Latency Expressions).

Constrain Latency only applies to subsystems which use the ChannelIn or ChannelOut blocks and not to subsystems that use the GPIn or GPOut blocks.

Show I/O time steps Turn on to display the datapath's pipeline time steps on the block mask of the GPIn, GPOut, ChannelIn and ChannelOut blocks in your design. Time steps, in clock cycles, are the delay from an arbitrary reference point (usually the start of the datapath) to the given point in the pipeline.
Simulation mode

Select a trade-off between simulation speed and simulation accuracy with one of the four options:

  • Use Global Value - use the value set on the drop-down menu Simulation Mode on the Simulation tab of the Control block.
  • Standard - a block-level simulation model that provides the fastest simulation with mathematical numerical accuracy. The default option.
  • Bit Accurate - a bit-accurate simulation model that more closely models the hardware, particularly for floating-point designs. The bit-accurate model models algorithmic delay but does not model latency balancing delay within the datapath. Instead, to approximate cycle-accuracy, DSP Builder applies a latency correction to the outputs. Scope values inside primitive subsystems may not be accurate when using this model, because the scope values are obtained from the Standard simulation, which runs in parallel to the bit-accurate model.
  • Bit and Cycle Accurate as for Bit Accurate but with cycle accuracy within the datapath. However, as for Bit Accurate, scope values may still not be accurate.
Local reset minimization

Select the reset minimization for the associated synthesizable subsystem. Valid only if Control block Global Enable is On.

The default is Conditional – On for ChannelIn/Out only.

Select Off to disable reset minimization on this synthesizable subsystem.

Select On – Always (for ChannelIn/Out or GPIn/Out to apply reset minimization to a synthesizable subsystem that uses GPIn/Out blocks. In a GPIn/Out subsystem with reset minimization, the whole subsystem is data flow and has no valid signal to be control flow.

The SynthesisInfo block has no inputs or outputs.