DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

6.4.1. Complex FIR Filter

This design example demonstrates how to implement a complex FIR filter using three real filters. The resource efficient implementation (three real multipliers per complex multiply) maps optimally onto Intel Arria 10 DSP blocks, using the scan and cascade modes.

The model file is demo_complex_fir.mdl.