DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents Adding a Finite State Machine Block to your DSP Builder Design

The simple.fsm file that you create specifies how the Finite State Machine block behaves in simulation.
Figure 132. Finite State Machine Simulation

The first state is always the initial state. The word after the state keyword is just a label. You can use any alphanumeric string instead of the word Start. It remains in this state while producing logic low (0) at the output if the x-input is logic low. When the x-input goes high, the Finite State Machine block goes logic high (1) and transitions to the next state. In all subsequent cycles the Finite State Machine ignores the x-input and remains in the second state always setting the output to low (0)


  1. Create a text file simple.fsm containing the following text:
    # A simple finite state machine
    require version 23.3
    inputs x
    transitions Simple : q
        state Start
            if (x) Next 1
        state Next
            default Next 0
  2. In the Simulink Library Browser, find the Finite State Machine block in DSP Builder for Intel FPGAs - Advanced Blockset > Primitives > Primitive Design Elements
    Figure 133. Simulink Library Browser
  3. Insert this block into a scheduled primitive subsystem in your design. The block initially has no ports for connecting wires.
  4. Double click on it to open its masked parameter dialog. Type the name of the text file you created earlier.
    Figure 134. Specify Model Description File Name
    Ports appear on the Finite State Machine block. One input port is x as you specify on the second line of the simple.fsm file. The name of the output port is derived from the names specified after the transitions keyword. The Finite State Machine block always has a go port. It remains in the starting state waiting for a logic high for one cycle on the go input. This port:
    • Should connect to the valid input signal. Because Simulink treats Boolean and ufix1 fixed-point types as distinct, you might have to use a Convert block with output set to Inherit via back-propagation. If your design has no equivalent to the valid signal, connect the go port to a Constant-1 block.
    • Allows connecting multiple Finite State Machine blocks in a chain so that when one Finite State Machine completes it passes a token (i.e. a logic high pulse) to the go port of the next Finite State Machine.
    Figure 135. Finite State Machine Block Ports