DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

15.2.2. HDL Import Config

The HDL Import Config block contains the top-level information to implement the HDL import feature. To use the HDL import feature, you must have one HDL Import Config block be at the top level of your design.
Figure 148. HDL Import Config

The HDL import feature needs the time relationship between ModelSim and Simulink. ModelSim uses the Control block-defined clock rate.
Table 285.  HDL Import Parameters
Parameter Description
Working Directory DSP Builder creates this working directory for the ModelSim library and other intermediate files.
Top-level instance

Enter the name of the top-level instance. If that instance is not the HDL you want to import but a wrapper for multiple instances, turn on Top-level is a wrapper.

Compile Click to compile imported RTL. Reclick if the imported RTL changes. For the cosimulation, DSP Builder creates a ModelSim library and performs ModelSim compilation followed by a series of Quartus synthesis compilations, one for each imported instance. The output from the compilations, including any errors, is printed to the MATLAB Command Window

The status light is yellow when the compile status is unknown, red when an error has occurred, and green on success. DSP Builder prints the compilation output to the MATLAB Command Window.

Simulink sample time Specify the sample time of the DSP Builder part of your Simulink model.
Reset cycles Allows you to hold your imported HDL in reset for an arbitrary number of cycles before the cosimulation begins.
Port The TCP/IP port number that the cosimulation uses for communication.