DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents

6.4.12. Interpolating FIR Filter

This design example uses the InterpolatingFIR block to build a 16-channel interpolate by 2, symmetrical, 49-tap FIR filter with a target system clock frequency of 240 MHz.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_firi.m script.

The FilterSystem subsystem includes the Device and InterpolatingFIR blocks.

The model file is demo_firi.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.