DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

6.2.7. Floating-Point iFFT

This design example implements a floating-point 512 point, radix 22 iFFT. This design example accepts bit-reversed order data at the input and produces natural order data at the output. The design example includes a BitReverseCoreC block. which converts the input data stream from natural order to bit-reversed order, and an FFT_Float block, which performs an FFT on bit-reversed data and produces its output in natural order.

The model file is demo_fpifft.mdl.