DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Document Table of Contents

3.4.5. Testing the Software Model

Before integrating a software model into another system or wrapping it as a MEX function, run the generated testbench to verify correctness. This task uses the demo_fft design as an example.


  1. Open the demo_fft design:
    Figure 30. demo_fftThe device-level of the design. The figure does not show Intermediate result signal outputs.
  2. Enable software model generation in the Control block's Simulation tab.
  3. Generate project files with CMake in the cmodel/build directory
  4. Compile and run the atb_app testbench, check for the success message:
    Info: [demo_fft_FFT_2K_t] Opening input stimulus files...
    Info: [demo_fft_FFT_2K_t] Simulating...
    Info: [demo_fft_FFT_2K_t] Simulation has completed.
    Info: [demo_fft_FFT_2K_t] Success! Software model matches Simulink simulation.
    Press any key to continue . . .
    Figure 31. demo_fft_compile