DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Public
Document Table of Contents

6.14. DSP Builder Reference Designs

DSP Builder also includes reference designs that demonstrate the design of DDC and DUC systems for digital intermediate frequency (IF) processing.

This folder accesses groups of reference designs that illustrate the design of DDC and DUC systems for digital intermediate frequency (IF) processing.

The first group implements IF modem designs compatible with the Worldwide Interoperability for Microwave Access (WiMAX) standard. Intel provides separate models for one and two antenna receivers and transmitters.

The second group implement IF modem designs compatible with the wideband Code Division Multiple Access (W-CDMA) standard.

This folder also contains reference designs.

STAP for radar systems applies temporal and spatial filtering to separate slow moving targets from clutter and null jammers. Applications demand highprocessing requirements and low latency for rapid adaptation. High-dynamic ranges demand floating-point datapaths.