DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents

3.1.4. Vectorized Inputs

Use vector data inputs and outputs for DSP Builder IP and Primitive library blocks when the clock rate is insufficiently high to carry the total aggregate data. For example, 10 channels at 20 MSPS require 10 × 20 = 200 MSPS aggregate data rate. If the system clock rate is set to 100 MHz, two wires must carry this data, and so the Simulink model uses a vector of width 2.

Unlike traditional methods, you do not need to manually instantiate two IP blocks and pass a single wire to each in parallel. Each IP block internally vectorizes. DSP Builder uses the same paradigm on outputs, where it represents high data rates on multiple wires as vectors.

Each IP block determines the input and output wire counts, based on the clock rate, sample rate, and number of channels.

Any rate changes in the IP block affect the output wire count. If a rate change exists, such as interpolating by two, the output aggregate sample rate doubles. DSP Builder packs the output channels into the fewest number of wires (vector width) that supports that rate. For example, an interpolate by two FIR filter may have two wires at the input, but three wires at the output.

The IP block performs any necessary multiplexing and packing. The blocks connected to the inputs and outputs must have the same vector widths, which Simulink enforces. Resolve vector width errors by carefully changing the sample rates.

Note: Most Primitive library blocks also accept vector inputs.