DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents

9.1.5. Using Automated Verification

To use automated verification, on the DSP Builder menu click Verify Design.

The testbench uses captured test vectors from the Simulink simulation and plays through the clock rate simulation of the generated hardware at the data rate. DSP Builder checks the order and bit-accuracy of the hardware simulation outputs against the Simulink simulation.