DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Public
Document Table of Contents

9.1.3. ALU Folding Simulation Rate

In the ALU folding parameters, you can specify Data rate or Clock rate for Simulation rate. the Simulation rate only controls the simulink simulation; the hardware is identical.

Date rate simulation offers the following features:

  • Simulates faster.
  • Simulates original unfolded model.
  • Each Simulink sample represents a data sample.
  • Generates automatic ModelSim testbench (if turned on in the Control block).

Clock rate simulation offers:

  • Simulink sample rates identical to the clock rate.
  • Simulation matches the hardware interface.
  • Modelling of clock level timings and jitter in the data inputs.

Data Rate

Figure 90. Single Channel Data Rate Simulation with no Register Outputs
Figure 91. Multichannel Data Rate Simulation with no Register OutputsThe Simulink sample time is a third of the data sample period

Clock Rate

Figure 92. Single Channel Clock Rate Simulation with no Register Outputs
Figure 93. Single Channel Clock Rate Simulation with Register Outputs
Figure 94. Multichannel Clock Rate Simulation with no Register Outputs
Figure 95. Multichannel Clock Rate Simulation with Register Outputs