DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

13.1.5. Register Bit (RegBit)

The DSP Builder RegBit block provides a register bit that you can read in your model and read or write with the processor interface.
Table 82.  Parameters for the RegBit Block
Parameter Description
Register Offset Specifies the address of the register. Must evaluate to an integer address.
Read/Write Mode Specifies the mode of the memory as viewed from the processor:
  • Read: processor can only read over specified address range.
  • Write: processor can only write over specified address range.
  • Read/Write: processor can read or write over specified address range.
  • Constant: processor cannot access specified address range. This option continues to reserve space in the memory map.
Bit Specifies the bit location of the memory-mapped register in a processor word (allows different registers to share same address).
Initial Value Specifies the initial state of the register. A 1-D vector specifies a vector of memory-mapped registers.
Description Text describing the register. The description is propagated to the generated memory map.
Sample Time Specifies the Simulink sample time.
Table 83.  Port Interface for the RegBit Block
Signal Direction Type Vector Support Complex Support Description
q Output Boolean or ufix(1) Yes Yes Data.