DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents

7.2.2. Closing Timed feedback Loops

Generally, take care with DSP Builder feedback loops, in particular you must provide sufficient algorithmic delay around the loop. In automatically pipelining designs, DSP Builder creates a schedule of signals through the design. From internal timing models, DSP Builder calculates how fast certain components, such as adders, can run and how many pipelining stages they require to run at a specific clock frequency. DSP Builder must account for the required pipelining while not changing the order of the schedule.

For example, a design that has a cycle containing two adders with only a single sample delay might not close timing in DSP Builder at some target clock frequency, because the single sample delay is not enough to pipeline the path through the two adders at that clock frequency.

DSP Builder is not free to insert more pipelining registers, as inserting more registers changes the algorithm. If the design does not have sufficient algorithmic delay, an error similar to the following may be reported in the Simulink diagnostics panel:

Message: error reported by s-function 'mip_control' in 'loop3/control':
Failure to redistribute delay in [loop3_subsystem] - tight clock constraints (0) loop3_subsystem_nestedloop3_or_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_and_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_not_x | loop3_subsystem | { }
(-1) loop3_subsystem_nestedloop3_and9_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_mcounter2_cmpeq_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_mcounter2_mux1_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_mcounter2_mux_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_and8_x | loop3_subsystem | { }
(0) loop3_subsystem_nestedloop3_and1_x | loop3_subsystem | { }

The sum of all the numbers in the parentheses at the beginning of each line is -1. This condition is known as a negative cycle and means that DSP Builder cannot close timing on the loop.

You have two possible solutions depending on the design:


  1. Reduce the target clock frequency until the error no longer occurs
  2. Add algorithmic latency to the loop by adding a SampleDelay block
    You may need to adjust other parts of your design to account for the extra delay in the feedback loop.