DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 4/01/2024
Document Table of Contents

14.6.4. Enabled Feedback Delay

The DSP Builder Enabled Feedback Delay block takes a single data signal a and an enable signal e and implements an enabled delay, with q as the delayed data output. The block is a non-enabled SampleDelay block followed by a FIFO buffer. When you use the block in a feedback loop, DSP Builder can distribute the non-enabled sample delay around the feedback path, while retaining the right enabled feedback behavior.