DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

1.7. Software and Hardware DSP Design Flows in FPGAs

Intel FPGAs with embedded processors support a software-based design flow. Intel provides the Nios® II EDS development tools for compiling, debugging, assembling, and linking software designs. You can then use either on-chip RAM or an external memory device to download these software designs to an FPGA.

Embedded processors and hardware acceleration offer the flexibility, performance, and cost effectiveness in a development flow that is familiar to software developers. You can combine a software design flow with hardware acceleration. In this flow, you first profile C code and identify the functions that are the most performance critical. Then, you can use Intel's DSP IP or develop your own custom instructions to accelerate those tasks in the FPGA. You can run the system control code with the other nonperformance-critical DSP algorithms on a Nios® II embedded processor. Intel also provides system integration tools such as Platform Designer for system-level partitioning and interconnection. You can use Platform Designer to build entire hardware systems by combining the embedded processor, such as a Nios® II embedded processor, with other system peripherals and IP.

You can use an HDL-based hardware design flow to develop a pure hardware implementation of a DSP system. Intel provides a complete set of FPGA development tools including the Quartus® Prime and interfaces to other EDA tools such as Synopsys, Synplify, and Precision Synthesis. These tools enable hardware design, simulation, debug, and in-system verification of the DSP system. You can also follow the DSP Builder for Intel® FPGAs design flow and implement hardware-only DSP systems in FPGAs without learning HDL.