DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

6.2.8. Floating-Point iFFT without BitReverseCoreC Block

This design example implements a floating-point 512 point, radix 22 iFFT. This design example accepts natural order data at the input and produces natural order data at the output. The design example is identical to the floating-point iFFT design example, but it does not include a BitReverseCoreC block, which converts the input data stream from natural order to bit-reversed order.

The model file is demo_fpifft_core.mdl.