DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

8.9. About Importing HDL

Importing HDL enables you to cosimulate existing HDL as a subsystem within your DSP Builder designs.

Importing HDL has the following software requirements:

  • HDL Verifier toolbox
  • An HDL Verifier compatible version of the ModelSim simulator (importing HDL does not support ModelSim AE)

Additionally, your HDL must conform to DSP Builder design rules and must:

  • Have only one clock domain
  • Match reset level with DSP Builder
  • Use the std_logic data type for clock and reset ports
  • Use std_logic_vector for all other ports
  • Have no top-level generics
  • Contain no bus components

    You may need to write a wrapper HDL file that instantiates your HDL, which might configure generics, convert from other data types to std_logic_vector, or invert the reset signal.

    DSP Builder can import any number of instantiated entities. To import multiple copies of an entity or multiple distinct entities, instantiate the entities in a top-level wrapper file.

    Simulink does not model all the signal states that ModelSim uses (e.g. ‘U’). Simulink interprets all non-‘1’ states as a ‘0’.

Importing HDL uses the HDL Verifier toolbox to communicate with an HDL simulation running in ModelSim. You can have as many components in your ModelSim simulation as you like; each component communicates with a separate DSP Builder HDL Import block. Your top-level design must include an HDL Import Config block.

Figure 89. HDL Import Block Placement

You cannot place HDL Import blocks inside a primitive scheduled subsystem.

DSP Builder creates the appropriate instantiation of the component represented by the HDL Import block.

DSP Builder sees imported HDL as a scheduled system. DSP Builder does not try to schedule your imported HDL. You cannot import HDL into a scheduled subsystem. Imported HDL acts like other DSP Builder IP blocks (e.g. NCO, FFT). You must manually delay-balance any parallel datapaths and turn on Generate Hardware in the Control block.