DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/11/2024
Document Table of Contents

6.12.4. 2-Channel DUC

This design example shows how to build a 2-channel DUC.

Interpolating CIC and FIR filters up convert a single complex channel (2 real channels). A NCO and Mixer subsystem combine the complex input channels into a single output channel.

This design example shows how quick and easy it is to emulate the contents of an existing datapath. A Mixer block implements the mixer in this design example as the data rate is low enough to save resource using a time-shared hardware technique.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_AD9856.m script.

The AD9856 subsystem includes a Device block and a lower level DUCIQ subsystem.

The DUCIQ subsystem includes Const, InterpolatingFIR, SingleRateFIR, InterpolatingCIC, NCO, Scale blocks, and a lower level Mixer subsystem.

The Mixer subsystem includes ChannelIn, ChannelOut, Mult, Const, BitExtract, CompareEquality, And, Delay, Sub, and SynthesisInfo blocks.

The model file is demo_AD9856.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.