Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

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31.4. Video Timing Generator IP Interfaces

The IP has one video output interface. You can configure the video output interface at build time to be either full-raster or Intel legacy clocked video interface. The IP has one optional processor interface.

The processor interface is asynchronous to the video output interface. The video clock can be unstable when you select a new standard, which can cause unreliable behavior if you use it for the processor interface.

The Intel FPGA streaming video full-raster protocol is compatible with AMBA AXI4-Stream interfaces to connect components that exchange video data. The protocols allow interfaces to Intel FPGA video IPs or other AXI4-Stream compliant third-party video IPs.

The video clock and processor clock are asynchronous to each other. Internally, the Video Timing Generator IP includes clock domain crossing (CDC) circuits for both single bit and data bus signal cases, which allows safe data exchange between the two asynchronous clock domains. The Video Timing Generator IP also includes an embedded entity .sdc file, which provides all the necessary information to the Intel Quartus Timing Analyzer. For system integration, when you instantiate the Video Timing Generator IP in a design, the only constraints required are:

  • Clock frequency constraints for the video clock (vid_clock_clk)
  • Clock frequency constraints for the processor clock (cpu_clock_clk)
Table 523.  Video Timing Generator output video interfaces
Signal name Direction Width Description
Clocks and resets
vid_clock_clk In 1 Output AXI4-S full-raster processing clock
vid_reset_reset in 1 Output AXI4-S full-raster processing reset
cpu_clock_clk in 1

Processor interface processing clock

cpu_reset_reset in 1

Processor interface processing reset

Control Interface

This interface is only available if you turn on Memory-Mapped Control Interface.

av_mm_cpu_agent_address Input 7 Control agent port Avalon memory-mapped address bus. Specifies a word offset into the slave address space.
av_mm_cpu_agent_read Input 1 Control agent port Avalon memory-mapped read signal. When you assert this signal, the control port drives new data onto the read data bus.
av_mm_cpu_agent_read_data_valid Output 1 Control agent port Avalon memory-mapped read data valid signal. The IP asserts this signal on the same clock cycle when the read data is valid.
av_mm_cpu_agent_readdata Output 32 Control agent port Avalon memory-mapped read data bus. These output lines are used for read transfers
av_mm_cpu_agent_waitrequest Output 1 Control agent port Avalon memory-mapped wait request bus. This signal indicates that the agent is stalling the master transaction.
av_mm_cpu_agent_write Input 1 Control agent port Avalon memory-mapped write signal. When you assert this signal, the control port accepts new data from the write data bus.
av_mm_cpu_agent_writedata Input 32 Control agent port Avalon memory-mapped write data bus. These input lines are used for writing transfers.
av_mm_cpu_agent_byteenable Input 4 Control agent port Avalon memory-mapped byteenable bus. These lines indicate which bytes are selected for write and read transactions.

Intel FPGA streaming video interfaces

axi4s_fr_vid_out_tdata out 90 91 AXI4-S data out
axi4s_fr_vid_out_tvalid out 1 AXI4-S data valid
axi4s_fr_vid_out_tuser[0] out 1 AXI4-S start of video frame
axi4s_fr_vid_out_tlast out 1 AXI4-S end of packet
axi4s_fr_vid_out_tready in 1 AXI4-S data ready

Intel FPGA CV-Lite Streaming Video Interface

This interface is only available if you set Output Type to CV on the Build Parameters tab

PIP = pixels in parallel

Port Name Direction Width Description
cv_vid_out_h Output PIP When 1, the video is in a horizontal blanking.
cv_vid_out_v Output PIP When 1, the video is in a vertical blanking.
cv_vid_out_h_sync Output PIP When 1, the video is in a horizontal synchronization period.
cv_vid_out_v_sync Output PIP When 1, the video is in a vertical synchronization period.
cv_vid_out_f Output PIP When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field 0.
cv_vid_out_active Output PIP When asserted, the video is in an active picture period (not horizontal or vertical blanking). You must drive this signal for correct operation of the IP.
cv_vid_out_data Output 92 Pixel data

90

The equation gives all full-raster tdata widths:

max (floor((( bits per color sample x (number of color planes+1) x pixels in parallel) + 7) / 8) x 8, 16)

91

The equation gives all tdata video active only sizes:

max (floor((( bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)

N = ceil (tdata width / 8)

92

The equation gives the data width:

width = (bits per color sample X number of color planes X pixels in parallel)