Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

21.1.1. Generic Crosspoint IP Features

  • Parameterizable 1 to 32 discrete input and output conduits
  • Optional Avalon memory-mapped processor control interface to program the crosspoint
  • Run-time and build-time crosspoint routing of inputs to outputs
  • Synchronous I/O interfaces only
  • 1 to 1024 bits port width configuration
  • Small FPGA resource footprint