Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 8/08/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Resampler Intel® FPGA IP 11. Clipper Intel® FPGA IP 12. Clocked Video Input Intel® FPGA IP 13. Clocked Video to Full-Raster Converter Intel® FPGA IP 14. Clocked Video Output Intel® FPGA IP 15. Color Space Converter Intel® FPGA IP 16. Deinterlacer Intel® FPGA IP 17. FIR Filter Intel® FPGA IP 18. Frame Cleaner Intel® FPGA IP 19. Full-Raster to Clocked Video Converter Intel® FPGA IP 20. Full-Raster to Streaming Converter Intel® FPGA IP 21. Generic Crosspoint Intel® FPGA IP 22. Genlock Signal Router Intel® FPGA IP 23. Guard Bands Intel® FPGA IP 24. Mixer Intel® FPGA IP 25. Pixels in Parallel Converter Intel® FPGA IP 26. Scaler Intel® FPGA IP 27. Tone Mapping Operator Intel® FPGA IP 28. Test Pattern Generator Intel® FPGA IP 29. Video Frame Buffer Intel® FPGA IP 30. Video Streaming FIFO Intel® FPGA IP 31. Video Timing Generator Intel® FPGA IP 32. Warp Intel® FPGA IP 33. Design Security 34. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Resampler Intel® FPGA IP x
10.1. About the Chroma Resampler IP 10.2. Chroma Resampler IP Parameters 10.3. Chroma Resampler IP Functional Description 10.4. Chroma Resampler IP Registers 10.5. Chroma Resampler IP Software API
10.1. About the Chroma Resampler IP x
10.1.1. Chroma Resampler Performance and Resources
10.3. Chroma Resampler IP Functional Description x
10.3.1. Chroma Resampler IP Interfaces
11. Clipper Intel® FPGA IP x
11.1. About the Clipper IP 11.2. Clipper IP Parameters 11.3. Clipper IP Interfaces 11.4. Clipper IP Registers 11.5. Clipper IP Software API
11.1. About the Clipper IP x
11.1.1. Clipper IP Performance and Resources
12. Clocked Video Input Intel® FPGA IP x
12.1. About the Clocked Video Input IP 12.2. Initializing the Clocked Video Input IP 12.3. Clocked Video Input IP Parameters 12.4. Clocked Video Input IP Interfaces 12.5. Clocked Video Input IP Registers 12.6. Clocked Video Input IP Software API
12.1. About the Clocked Video Input IP x
12.1.1. Clocked Video Input IP Features 12.1.2. Clocked Video Input IP Performance and Resources
13. Clocked Video to Full-Raster Converter Intel® FPGA IP x
13.1. About the Clocked Video to Full-Raster Converter IP 13.2. Clocked Video to Full-Raster Converter Parameters 13.3. Clocked Video to Full-Raster Converter Block Description 13.4. Clocked Video Converter to Full-Raster IP Registers
13.1. About the Clocked Video to Full-Raster Converter IP x
13.1.1. Clocked Video to Full-Raster Converter Features 13.1.2. Clocked Video to Full-Raster Converter Performance and Resources
13.3. Clocked Video to Full-Raster Converter Block Description x
13.3.1. Clocked Video to Full-Raster Converter Interfaces
14. Clocked Video Output Intel® FPGA IP x
14.1. About the Clocked Video Output IP 14.2. Clocked Video Output IP Parameters 14.3. Clocked Video Output IP Functional Description 14.4. Clocked Video Output IP Interfaces 14.5. Clocked Video Output IP Registers 14.6. Clocked Video Output IP Software API
14.1. About the Clocked Video Output IP x
14.1.1. Clocked Video Output IP Performance and Resources 14.1.2. Clocked Video Output IP Features
15. Color Space Converter Intel® FPGA IP x
15.1. About the Color Space Converter IP 15.2. Color Space Converter IP Parameters 15.3. Color Space Converter IP Functional Description 15.4. Color Space Converter IP Registers 15.5. Color Space Converter IP Software API
15.1. About the Color Space Converter IP x
15.1.1. Color Space Converter IP Features 15.1.2. Color Space Converter IP Performance and Resources
15.3. Color Space Converter IP Functional Description x
15.3.1. Color Space Converter IP Interfaces
16. Deinterlacer Intel® FPGA IP x
16.1. About the Deinterlacer IP 16.2. Deinterlacer Parameters 16.3. Deinterlacer Interfaces 16.4. Deinterlacer Registers 16.5. Deinterlacer IP Software API
16.1. About the Deinterlacer IP x
16.1.1. Deinterlacer Performance and Resources
17. FIR Filter Intel® FPGA IP x
17.1. About the FIR Filter 17.2. FIR Filter Parameters 17.3. FIR Filter IP Operation 17.4. FIR Filter Interfaces 17.5. FIR Filter Registers 17.6. FIR Filter IP Software API
17.3. FIR Filter IP Operation x
17.3.1. FIR Filter Processing 17.3.2. FIR Filter Precision 17.3.3. FIR Coefficient Specification 17.3.4. FIR Filter Symmetry 17.3.5. Result to Output Data Type Conversion
17.3.4. FIR Filter Symmetry x
17.3.4.1. No Symmetry 17.3.4.2. Horizontal Symmetry 17.3.4.3. Vertical Symmetry 17.3.4.4. Horizontal and Vertical Symmetry 17.3.4.5. Diagonal Symmetry
18. Frame Cleaner Intel® FPGA IP x
18.1. About the Frame Cleaner IP 18.2. Frame Cleaner IP Parameters 18.3. Frame Cleaner IP Functional Description 18.4. Frame Cleaner IP Interfaces 18.5. Frame Cleaner IP Registers 18.6. Frame Cleaner IP Software API
18.1. About the Frame Cleaner IP x
18.1.1. Frame Cleaner IP Performance and Resources
19. Full-Raster to Clocked Video Converter Intel® FPGA IP x
19.1. About the Full-Raster to Clocked Video Converter 19.2. Full Raster to Clocked Video Converter Parameters 19.3. Full-Raster to Clocked Video Converter Block Description 19.4. Full-Raster to Clocked Video Converter Registers
19.1. About the Full-Raster to Clocked Video Converter x
19.1.1. Full-Raster to Clocked Video Converter Features 19.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
19.3. Full-Raster to Clocked Video Converter Block Description x
19.3.1. Full Raster to Clocked Video Converter Interfaces
20. Full-Raster to Streaming Converter Intel® FPGA IP x
20.1. About the Full-Raster to Streaming Converter IP 20.2. Full-Raster to Streaming Converter Parameters 20.3. Full-Raster to Streaming Converter Block Description
20.1. About the Full-Raster to Streaming Converter IP x
20.1.1. Full-Raster to Streaming Converter Features 20.1.2. Full-Raster to Streaming Converter Performance and Resources
20.3. Full-Raster to Streaming Converter Block Description x
20.3.1. Full-Raster to Streaming Converter Interfaces
21. Generic Crosspoint Intel® FPGA IP x
21.1. About the Generic Crosspoint IP 21.2. Generic Crosspoint IP Parameters 21.3. Generic Crosspoint IP Interfaces 21.4. Generic Crosspoint IP Registers 21.5. Generic Crosspoint IP Software API
21.1. About the Generic Crosspoint IP x
21.1.1. Generic Crosspoint IP Features 21.1.2. Generic Crosspoint Performance and Resources
22. Genlock Signal Router Intel® FPGA IP x
22.1. About the Genlock Signal Router IP 22.2. Genlock Signal Router IP Parameters 22.3. Genlock Signal Router IP Interfaces 22.4. Genlock Signal Router IP Registers 22.5. Genlock Signal Router IP Software API
22.1. About the Genlock Signal Router IP x
22.1.1. Genlock Signal Router IP Features 22.1.2. Genlock Signal Router IP Performance and Resources
23. Guard Bands Intel® FPGA IP x
23.1. About the Guard Bands IP 23.2. Guard Bands IP Parameters 23.3. Guard Bands IP Interfaces 23.4. Guard Bands IP Registers 23.5. Guard Bands IP Software API
23.1. About the Guard Bands IP x
23.1.1. Guard Bands IP Performance and Resources
24. Mixer Intel® FPGA IP x
24.1. About the Mixer IP 24.2. Mixer IP Parameters 24.3. Mixer IP Functional Description 24.4. Mixer IP Registers 24.5. Mixer IP Software API
24.1. About the Mixer IP x
24.1.1. Mixer IP Performance and Resources
24.3. Mixer IP Functional Description x
24.3.1. Mixer IP Interfaces
25. Pixels in Parallel Converter Intel® FPGA IP x
25.1. About the Pixels in Parallel Converter IP 25.2. Pixels in Parallel IP Converter Parameters 25.3. Pixels in Parallel Converter Interfaces 25.4. Pixels in Parallel Converter Registers 25.5. Pixels in Parallel Converter IP Software API
25.1. About the Pixels in Parallel Converter IP x
25.1.1. Pixels in Parallel IP Converter Performance and Resources
26. Scaler Intel® FPGA IP x
26.1. About the Scaler 26.2. Scaler IP Parameters 26.3. Scaler IP Functional Description 26.4. Scaler IP Registers 26.5. Scaler IP Software API
26.1. About the Scaler x
26.1.1. Scaler IP Performance and Resources
26.2. Scaler IP Parameters x
26.2.1. Updating Scaler IP Runtime Coefficients 26.2.2. Scaler Maximum Resolution
26.3. Scaler IP Functional Description x
26.3.1. Partial Frame Scaling 26.3.2. Scaler IP Interfaces
27. Tone Mapping Operator Intel® FPGA IP x
27.1. About the Tone Mapping Operator IP 27.2. TMO IP Parameters 27.3. TMO IP Block Description 27.4. TMO IP Registers 27.5. TMO IP Software API
27.1. About the Tone Mapping Operator IP x
27.1.1. TMO IP Features 27.1.2. TMO IP Performance and Resource Utilization
27.3. TMO IP Block Description x
27.3.1. TMO IP Interfaces 27.3.2. TMO IP Latency
28. Test Pattern Generator Intel® FPGA IP x
28.1. About the Test Pattern Generator IP 28.2. Test Pattern Generator IP Parameters 28.3. Test Pattern Generator IP Functional Description 28.4. Test Pattern Generator IP Registers 28.5. Test Pattern Generator IP Software API
28.1. About the Test Pattern Generator IP x
28.1.1. Test Pattern Generator IP Performance and Resources
28.3. Test Pattern Generator IP Functional Description x
28.3.1. Test Pattern Generator IP Interfaces
29. Video Frame Buffer Intel® FPGA IP x
29.1. About the Video Frame Buffer IP 29.2. Video Frame Buffer IP Parameters 29.3. Video Frame Buffer IP Functional Description 29.4. Video Frame Buffer IP Registers 29.5. Video Frame Buffer IP Software API
29.1. About the Video Frame Buffer IP x
29.1.1. Video Frame Buffer Performance and Resources
29.3. Video Frame Buffer IP Functional Description x
29.3.1. Video Frame Buffer IP Interfaces
30. Video Streaming FIFO Intel® FPGA IP x
30.1. About the Video Streaming FIFO IP 30.2. Video Streaming FIFO IP Parameters 30.3. Video Streaming FIFO IP Interfaces
30.1. About the Video Streaming FIFO IP x
30.1.1. Video Streaming FIFO IP Performance and Resources
31. Video Timing Generator Intel® FPGA IP x
31.1. About the Video Timing Generator IP 31.2. Video Timing Generator IP Parameters 31.3. Video Timing Generator IP Functional Description 31.4. Video Timing Generator IP Interfaces 31.5. Video Timing Generator IP Registers 31.6. Video Timing Generator IP Software API
31.1. About the Video Timing Generator IP x
31.1.1. Video Timing Generator IP Features 31.1.2. Video Timing Generator IP Performance and Resources
32. Warp Intel® FPGA IP x
32.1. About the Warp IP 32.2. Warp IP Parameters 32.3. Warp IP Block Description 32.4. Warp IP Registers 32.5. Warp IP Software API
32.1. About the Warp IP x
32.1.1. Warp IP Features 32.1.2. Warp IP Performance and Resource Utilization
32.3. Warp IP Block Description x
32.3.1. Warp IP Interfaces 32.3.2. Warp IP Latency 32.3.3. External Memory for Warp IP
32.5. Warp IP Software API x
32.5.1. Using Warp IP Software 32.5.2. Warp IP Software Code Examples
33. Design Security x
33.1. Memory Subsystems 33.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Resampler Intel® FPGA IP
11. Clipper Intel® FPGA IP
12. Clocked Video Input Intel® FPGA IP
13. Clocked Video to Full-Raster Converter Intel® FPGA IP
14. Clocked Video Output Intel® FPGA IP
15. Color Space Converter Intel® FPGA IP
16. Deinterlacer Intel® FPGA IP
17. FIR Filter Intel® FPGA IP
18. Frame Cleaner Intel® FPGA IP
19. Full-Raster to Clocked Video Converter Intel® FPGA IP
20. Full-Raster to Streaming Converter Intel® FPGA IP
21. Generic Crosspoint Intel® FPGA IP
22. Genlock Signal Router Intel® FPGA IP
23. Guard Bands Intel® FPGA IP
24. Mixer Intel® FPGA IP
25. Pixels in Parallel Converter Intel® FPGA IP
26. Scaler Intel® FPGA IP
27. Tone Mapping Operator Intel® FPGA IP
28. Test Pattern Generator Intel® FPGA IP
29. Video Frame Buffer Intel® FPGA IP
30. Video Streaming FIFO Intel® FPGA IP
31. Video Timing Generator Intel® FPGA IP
32. Warp Intel® FPGA IP
33. Design Security
34. Document Revision History for Video and Vision Processing Suite User Guide

11.5. Clipper IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_clipper_regs.h

Include file: intel_vvp_clipper.h

Table 101.  Clipper API Reference
Name Description
intel_vvp_clipper_init Initialize the Clipper instance
Intel_vvp_core_* .Accessors defined in Video and Vision Processing IPs Software Programming Model . Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_clipper_get_lite_mode Returns if Lite mode is on
intel_vvp_clipper_get_debug_enabled Returns if Debug features is on
Intel_vvp_clipper_get_clipping_mode Returns the run-time clipping method
intel_vvp_clipper_is_running Returns if the IP is processing data
Intel_vvp_clipper_get_commit_status Returns if the IP has uncommitted writes
intel_vvp_clipper_get_status Reads the status register
intel_vvp_clipper_set_left_offset Writes new value to the left offset register
intel_vvp_clipper_set_top_offset Writes new value to the top offset register
intel_vvp_clipper_set_right_offset Writes new value to the right offset register
intel_vvp_clipper_set_bottom_offset Writes new value to the bottom offset register
intel_vvp_clipper_set_clip_offsets Writes new values to the four offset registers
intel_vvp_clipper_set_clip_width Writes new value to the clipping width register
intel_vvp_clipper_set_clip_height Writes new value to the clipping height register
intel_vvp_clipper_set_clip_area Writes new values to the offset/clip registers
intel_vvp_clipper_get_left_offset Reads the left offset register
intel_vvp_clipper_get_top_offset Reads the top offset register
intel_vvp_clipper_get_right_offset Reads the right offset register
intel_vvp_clipper_get_bottom_offset Reads the bottom offset register
intel_vvp_clipper_get_clip_offsets Reads the four offset registers
intel_vvp_clipper_get_clip_width Reads the clipping width register
intel_vvp_clipper_get_clip_height Reads the clipping height register
intel_vvp_clipper_get_clip_area Reads the offset and clip registers
intel_vvp_clipper_commit_writes Commit all outstanding writes

enum eIntelVvpClippingMode

Members

kIntelVvpOffsetClipping – Clipping with four offsets from the input borders

kIntelVvpRectangleClipping – Clipping with a top-left offset and the dimensions of the clipped area

kIntelVvpInvalidClipping – Invalid clipping (used to indicate errors)

Description
Enumeration for the supported clipping methods

intel_vvp_clipper_init

Prototype
int intel_vvp_clipper_init(intel_vvp_clipper_instance *instance, intel_vvp_core_base base);
Description

Initializes a clipper instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance does not fully initialized and should not be used further by the application if returning a non-zero error code.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

base – base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the TPG product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpClipperRegMapVersionErr if the register map is not supported

intel_vvp_clipper_get_lite_mode

Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_clipper_instance fully initialized

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_clipper_get_debug_enabled

Prototype
bool intel_vvp_clipper_get_debug_enabled(intel_vvp_clipper_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_clipper_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_clipper_get_clipping_mode

Prototype
eIntelVvpClippingMode intel_vvp_clipper_get_clipping_mode(intel_vvp_clipper_instance *instance);
Description

Returns the value of the CLIPPING_MODE register. The instance must be a valid intel_vvp_clipper_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

the clipping mode or kIntelVvpInvalidClipping in case of error

intel_vvp_clipper_is_running

Prototype
bool intel_vvp_ clipper _is_running(intel_vvp_clipper_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_clipper_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

True is the IP is currently generating an output field, false when between two fields

intel_vvp_clipper_get_commit_status

Prototype
bool intel_vvp_clipper_get_commit_status(intel_vvp_clipper_instance* instance);
Description

Reads and returns the commit pending bit of the STATUS register. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured in full mode.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

True is the IP is configured in full mode and if the agent interface contains uncommitted writes.

intel_vvp_clipper_get_status

Prototype
uint8_t intel_vvp_clipper_get_status(intel_vvp_clipper_instance* instance);
Description

Reads and returns the STATUS register. The instance must be a valid intel_vvp_clipper_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

The value read from the status register

intel_vvp_clipper_set_left_offset

Prototype
int intel_vvp_clipper_set_left_offset(intel_vvp_clipper_instance* instance , uint16_t left_offset);
Description

Writes a new offset value to the LEFT_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

left_offset – new left offset value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_top_offset

Prototype
int intel_vvp_clipper_set_top_offset(intel_vvp_clipper_instance* instance , uint16_t top_offset);
Description

Writes a new offset value to the TOP_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

top_offset – new top offset value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_right_offset

Prototype
int intel_vvp_clipper_set_right_offset(intel_vvp_clipper_instance* instance , uint16_t right_offset);
Description

Writes a new offset value to the RIGHT_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured for clipping with four offsets

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

right_offset – new right offset value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_bottom_offset

Prototype
int intel_vvp_clipper_set_bottom_offset(intel_vvp_clipper_instance* instance , uint16_t bottom_offset);
Description

Writes a new offset value to the BOTTOM_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured for clipping with four offsets

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

bottom_offset – new bottom offset value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_clip_offsets

Prototype
int intel_vvp_clipper_set_clip_offsets(intel_vvp_clipper_instance* instance , uint16_t left_offset, uint16_t top_offset, uint16_t right_offset, uint16_t bottom_offset);
Description

Writes new offsets value to the four offset registers. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured for clipping with four offsets

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

left_offset – new left offset value

top_offset – new top offset value

right_offset – new right offset value

bottom_offset – new bottom offset value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_clip_width

Prototype
int intel_vvp_clipper_set_clip_width(intel_vvp_clipper_instance *instance, uint32_t clip_width)
Description

Writes a new clipping width value to the CLIP_WIDTH register. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured for clipping with two offsets and dimensions of the clipped area

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

clip_width – new clipped area width value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_clip_height

Prototype
int intel_vvp_clipper_set_clip_height(intel_vvp_clipper_instance *instance, uint32_t clip_height)
Description

Writes a new clipping height value to the CLIP_HEIGHT register. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured for clipping with two offsets and dimensions of the clipped area

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

clip_height – new clipped area height value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_set_clip_area

Prototype
int intel_vvp_clipper_set_clip_area(intel_vvp_clipper_instance *instance, uint16_t left_offset , uint16_t top_offset , uint32_t clip_width, uint32_t clip_height)
Description

Writes new offsets and new dimensions to the offset and clipping registers. The instance must be a valid intel_vvp_clipper_instance fully initialized and configured for clipping with two offsets and dimensions of the clipped area

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

left_offset – new left offset value

top_offset – new top offset value

clip_width – new clipped area width value

clip_height – new clipped area height value

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_clipper_get_left_offset

Prototype
uint16_t intel_vvp_clipper_get_left_offset(intel_vvp_clipper_instance* instance);
Description

Reads the LEFT_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

The left offset value

intel_vvp_clipper_get_top_offset

Prototype
uint16_t intel_vvp_clipper_get_top_offset(intel_vvp_clipper_instance* instance);
Description

Reads the TOP_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized and parameterized with debug features enabled

Arguments
instance – pointer to the intel_vvp_clipper_instance software driver instance structure
Returns

The top offset value

intel_vvp_clipper_get_right_offset

Prototype
uint16_t intel_vvp_clipper_get_right_offset(intel_vvp_clipper_instance* instance);
Description

Reads the RIGHT_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized, configured for clipping with four offsets, and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

The right offset value

intel_vvp_clipper_get_bottom_offset

Prototype
uint16_t intel_vvp_clipper_get_bottom_offset(intel_vvp_clipper_instance* instance);
Description

Reads the BOTTOM_OFFSET register. The instance must be a valid intel_vvp_clipper_instance fully initialized, configured for clipping with four offsets, and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

The bottom offset value

intel_vvp_clipper_get_clip_offsets

Prototype
int intel_vvp_clipper_get_clip_offsets(intel_vvp_clipper_instance* instance , uint16_t *left_offset, uint16_t *top_offset, uint16_t *right_offset, uint16_t *bottom_offset);
Description

Read current offsets value from the four offset registers. The instance must be a valid intel_vvp_clipper_instance fully initialized, configured for clipping with four offsets, and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

left_offset – pointer to a uint16_t value to store the value read from the LEFT_OFFSET register

top_offset – pointer to a uint16_t value to store the value read from the TOP_OFFSET register

right_offset – pointer to a uint16_t value to store the value read from the RIGHT_OFFSET register

bottom_offset – pointer to a uint16_t value to store the value read from the BOTTOM_OFFSET register

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

kIntelVvpCoreNullPtrErr if one of the pointers to store an output value is the null pointer

intel_vvp_clipper_get_clip_width

Prototype
uint32_t intel_vvp_clipper_get_clip_width(intel_vvp_clipper_instance *instance)
Description

Reads the CLIP_WIDTH register. The instance must be a valid intel_vvp_clipper_instance fully initialized, configured for clipping with top-left offsets and dimensions of the clipped area, and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

Current clipping with value

intel_vvp_clipper_get_clip_height

Prototype
uint32_t intel_vvp_clipper_get_clip_height(intel_vvp_clipper_instance *instance)
Description

Reads the CLIP_HEIGHT register. The instance must be a valid intel_vvp_clipper_instance fully initialized, configured for clipping with top-left offsets and dimensions of the clipped area, and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

Current clipping height value

intel_vvp_clipper_get_clip_area

Prototype
int intel_vvp_clipper_get_clip_area(intel_vvp_clipper_instance *instance, uint16_t *left_offset , uint16_t *top_offset , uint32_t *clip_width, uint32_t *clip_height)
Description

Reads current top-left offset value from the two offset registers and dimensions of the clipped area from the clipping dimensions registers. The instance must be a valid intel_vvp_clipper_instance fully initialized, configured for clipping with top-left offsets and dimensions of the clipped area, and parameterized with debug features enabled

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

left_offset – pointer to a uint16_t value to store the value read from the LEFT_OFFSET register

top_offset – pointer to a uint16_t value to store the value read from the TOP_OFFSET register

right_offset – pointer to a uint32_t value to store the value read from the CLIP_WIDTH register

bottom_offset – pointer to a uint32_t value to store the value read from the CLIP_HEIGHT register

Returns

kIntelVvpCoreOk in case of success, negative value in case of errors

kIntelVvpCoreInstanceErr if the instance is invalid

kIntelVvpCoreNullPtrErr if one of the pointers to store an output value is the null pointer

intel_vvp_clipper_commit_writes

Prototype
int intel_vvp_clipper_commit_writes(intel_vvp_clipper_instance* instance)
Description

Commits all pending writes before processing the next field. The instance must be valid and parameterized in full mode.

Arguments

instance – pointer to the intel_vvp_clipper_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

Related Information
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