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9.1. About the AXI-Stream Broadcaster IP
The broadcast logic replicates the video streaming input bus to N outputs. You specify N at build time. The IP offers full, lite, and full-raster variants of Intel FPGA streaming video. For more information, refer to the Intel FPGA Streaming Video Protocol Specification.
To process TREADY backpressure on the output interfaces, each output has either a FIFO buffer of configurable depth, or a shim, which is equivalent to a 1-depth FIFO buffer. If an output deasserts its TREADY, its FIFO buffer continues to accept input until it is full. If any one of the output FIFO buffers is full and you turn on Global stall, the broadcaster stalls the input by deasserting its TREADY. The IP stops new input from filling any of the FIFO buffers until all the FIFO buffers are ready to accept new data. If you turn off Global stall option, the broadcaster input never stalls but the FIFO buffers drop new input when they are full. In either case, each output always asserts TVALID when data is present in its FIFO buffer.
Typically, you use full-raster variants for real-time video. The input and output TREADY signals are entirely optional. Disabling TREADY on any interface removes the signal and stops any backpressure on that interface. For outputs, this action replaces the FIFO buffer with a simple register stage. If you do not turn on TREADY on any of the outputs, global stall has no effect and the IP removes the option.
With these different backpressure options available, you consider the system design and determine what amount of backpressure is acceptable on each interface. For example, a processing pipeline operating on non-real-time video streams might want the global stall option. However, in a system where the broadcaster is dealing with real-time video, stalling the input might be unacceptable. Output FIFO buffers must be large enough so that no pushback reaches the broadcaster.
AXI-Stream Broadcaster IP Features
AXI-Stream Broadcaster IP Performance and Resources
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