Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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18.1. About the Frame Cleaner IP

The Intel FPGA Streaming Video protocol allows for the transmission of video fields that do not conform to expected width and height values (field size mismatch errors). The IP removes field size mismatch errors by ensuring that every field matches the expected width and height. The IP either crops or pads errant fields to match the values specified. The IP can use both the full and lite variants of the Intel FPGA Streaming Video protocol.

Every IP in the Video and Vision Processing Suite is tolerant of field size mismatch errors, so including the Frame Cleaner IP in a pipeline built entirely from Intel IPs is not necessary. It can help in the debug processes when building and testing a video pipeline.

If you choose to write your own Intel FPGA streaming video compliant IPs, you may add the Frame Cleaner IP to the pipeline at the input to your IPs. The IP allows you to write the code for your IPs without considering their behavior in all the potential error cases.