Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

21.1. About the Generic Crosspoint IP

The IP is a M x N generic data crosspoint where M and N signify the number of input and output ports, respectively. This IP can route discrete signals around an FPGA design under software control. Both input and output ports work on the same clock domain.
Data is input to and output from the Generic Crosspoint IP via a selectable number of ports. The size of the input and output ports is a global parameter configurable from the GUI. The number of input and output ports is in the range of 1 to 32.
Figure 53. Generic Crosspoint Block Diagram

The front-end and back-end of this IP include a bank of registers, and the crosspoint multiplexer and routing logic, which can process run-time and build-time configurable routing between input and output ports.

You can control the input-to-output routing dynamically at run-time via the CPU interface. You can also assign a default routing at build-time via the Platform Designer IP GUI. The crosspoint routing reverts to the default routing on reset. If you turn off the CPU interface, the crosspoint is statically fixed at the default routing, which you can use if the routing does not need to change at run-time.