Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

12.1.1. Clocked Video Input IP Features

  • An Avalon memory-mapped control interface
  • User configurable 1 to 32 clocked video input interfaces
  • Full-raster compliant video input interface
  • Intel FPGA streaming video compliant output interface (lite variant support only)
  • Optional TREADY conduit on the full-raster interface
  • Clock domain crossing between video pixel clock and video processing clock
  • 1K to 32K depth video line buffer
  • 8-bit to 16-bit per color component
  • 1, 2, 3, and 4 color planes per pixel
  • 1, 2, 4, and 8 pixels in parallel
  • Small FPGA resource footprint